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Azeem Rahman K
RTL Design Engineer at Capgemini | RTL Design | Verilog | SV | Linux | ASIC | FPGA | CPLD |
Education Overview
• apj abdul kalam technological university
Companies Overview
• capgemini
• maven silicon
Experience Overview
4.3 Years
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Experience
Skills
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5G
Arabic
asic
AXI
C (Programming Language)
Complex Programmable Logic Device (CPLD)
Design
DFT
Digital Electronics
Electronic Engineering
English
Field-Programmable Gate Arrays (FPGA)
FPGA
Gen 3 5g code
Lattice diamond
Linux
linux
Malayalam
Model sim
Object-Oriented Programming (OOP)
Python
Python (Programming Language)
Quarters prime
QuestaSim
RTL Coding
RTL Design
RTL Verification
Static Timing Analysis
SystemVerilog
Tamil
TCL
Universal Verification Methodology (UVM)
Verilog
Very-Large-Scale Integration (VLSI)
VHDL
vlsi
Xilinx ISE
Xilinx Vivado
Contact Details
Email (Verified)
azeXXXXXXXXXXXXXXXXXXomMobile Number
+91XXXXXXXX04Education
apj abdul kalam technological university
BTech-Bachelor of Technology
2016 - 2020
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